VLSI implementation of a 2.8 Gevent/s packet based AER interface with routing and event sorting functionality
State-of-the-art large scale neuromorphic systems require sophisticated spike event communication between units of the neural network.We present a high-speed communication Mugs infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an FPGA-maintained environment.The ICs implement configu